1. Field of the Invention
The present invention relates to a display apparatus, a control method of the same, and a projection type display apparatus, more particularly relates to a display and a projection type display (projector) employing the system of writing video signals in parallel by a plurality of pixels at a time in a horizontal direction (column array direction) in a display unit having pixels arrayed in a matrix.
2. Description of the Related Art
In a display, for example a liquid crystal display (LCD) using liquid crystal cells as display elements of the pixels, it is generally used a digital signal processing IC formed by an MOS process of a gate array as a signal processing system. The digital data subjected to predetermined signal processing by this digital signal processing IC is converted to an analog signal by a digital/analog (D/A) converter, then given to a liquid crystal panel (hereinafter described as an “LCD panel”) via an LCD driver. The LCD panel is provided with pixels including liquid crystal cells arrayed in a matrix.
The write speed of an LCD panel is not fast enough to enable sequentially writing of input video signals by one dot (pixel) at a time, therefore, in general, a method of writing video signals in parallel by a plurality of pixels at a time in the horizontal direction is employed. In an LCD of this simultaneous pixel write system, it is necessary to convert video signals sequentially input in a time sequence to a plurality of pixels' worth of the parallel signals for writing the video signals in parallel to a plurality of pixels.
For example, in a case of an LCD of a six-pixel simultaneous write system for writing pixels by six pixels at a time in parallel in the horizontal direction, video signals input in time sequence are converted to six parallel video signals so that the six pixels have the same timing. The video signals are written in parallel into six columns of signal lines in six pixels' worth of time. This parallel processing is carried out when sampling/holding the video signals in the LCD driver.
A sample/hold pulse used for this parallel processing is generated as a timing signal synchronized with a horizontal synchronization signal. Further, signal lines for transmitting six parallel video signals are physically connected to the LCD panel as interconnects. Therefore, the start position of the image is unambiguously determined by the above timing signal and a display start timing signal to the LCD panel.
On the other hand, inside the LCD panel, in order to write six pixels at a time in parallel, signal line selection switches for selecting six signal lines at a time in parallel are provided in units of six signal lines. Then, these signal line selection switches are sequentially selected by switch pulses (write signals) sequentially generated in synchronization with the video signals. By the signal line selection switches being sequentially selected, video signals are written into six signal lines in parallel through the selected signal line selection switches.
Here, inside the LCD panel, the switch pulses and the video signals are distorted due to the influence of the resistances or the capacitances of the signal lines for transmitting them, therefore, an optimum display image cannot be obtained unless the phase relationships between these switch pulses and video signals are adjusted. When the optimum phase relationship is not exhibited, the video signals leak before or after the six pixels adjacent to the position where they should originally exist, so end up forming double images. For example, when displaying one vertical line, if this phase relationship is off, the vertical line will also be displayed before or after the six pixels from the position where they should originally exist.
For this reason, in the past, technology has been proposed enabling adjustment of the phase relationships between the timing signal for the simultaneous write operation, that is, the switch pulses (write signals), and the video signals with a dot clock precision or more without changing the center position of the image (refer to for example Japanese Unexamined Patent Publication (Kokai) No. 2002-108299 (particularly paragraphs 0039 to 0049 and FIG. 7)). This prior art calls for adjusting the phase of the pulse signal serving as the reference of the generation of the switch pulse at the timing generation circuit so as to enable the adjustment of the phase relationships between the video signals and the switch pulses with a dot clock precision or more without changing the center position of the image.
The prior art was effective for adjustment of the phase relationships between the write signals for the simultaneous write operation and the video signals at the LCD before shipping, but could not deal with the deviation of the phase relationships between the two after shipping. Namely, even if optimum phase adjustment is possible before shipping, if the circuit elements deteriorate due to a temperature change or aging, delays end up occurring in liquid crystal drive pulses due to this, so the phase relationships become off and the optimum display image can no longer be obtained.